1. Technical Field
The present invention relates to an electrostatic discharge protection circuit for protecting a semiconductor integrated circuit from electrostatic discharge, and a semiconductor circuit device.
2. Related Art
When electric charges generated by electrostatic discharge (ESD) are applied to a semiconductor integrated circuit, elements incorporated in the semiconductor integrated circuit may be damaged. To address this, a technique has been proposed to protect the elements in the semiconductor integrated circuit by providing an electrostatic discharge protection circuit to the semiconductor integrated circuit, and discharging the electric discharges generated by ESD by using the electrostatic discharge protection circuit.
FIG. 10 is a diagram showing a configuration of an electrostatic discharge protection circuit proposed by US-A1-2006/0039093.
The electrostatic discharge protection circuit shown in FIG. 10 is included in a semiconductor integrated circuit. The electrostatic discharge protection circuit, which is connected to a direct-current power supply (not shown), includes a first power supply line 1100-1 having a power supply voltage potential VDD and a second power supply line 1100-2 having a potential VSS that is lower than the potential VDD. The second power supply line 1100-2 is connected to a frame ground GND.
The electrostatic discharge protection circuit also includes a time constant circuit 1101 composed of a resistor 1101a and a capacitor 1101b that are connected in series between the first power supply line 1100-1 and the second power supply line 1100-2.
The electrostatic discharge protection circuit also includes a relatively large-sized N-channel transistor 1102 that is connected between the first power supply line 1100-1 and the second power supply line 1100-2.
The electrostatic discharge protection circuit also includes three inverters 1103, 1104 and 1105 that are connected in series between a connection node located between the resistor 1101a and the capacitor 1101b and a gate of the N-channel transistor 1102.
An ESD event occurs due to electrostatic electricity being charged on the human body or a transporting device during transport of a semiconductor integrated circuit and flowing through the semiconductor integrated circuit. At first, the first power supply line 1100-1 has a potential equal to that of the second power supply line 1100-2. It is assumed here that, as an ESD event, positive ESD surge is applied to the first power supply line 1100-1 relative to the second power supply line 1100-2. Electric charges generated by the ESD surge are charged into the capacitor 1101b via the resistor 1101a. Here, the value of an RC time constant determined by the resistance value of the resistor 1101a and the capacitance value of the capacitor 1101b is large enough that an input-side node of the inverter 1103 is maintained at ‘L’ level during a time period corresponding to the RC time constant. In a state in which the input-side node of the inverter 1103 is maintained at ‘L’ level, the gate of the N-channel transistor 1102 is at ‘H’ level via the inverters 1104 and 1105. Accordingly, the N-channel transistor 1102 is brought into an ON state. In this way, as a result of the surge current escaping through the N-channel transistor 1102, it is possible to prevent high voltage from being applied between the first power supply line 1100-1 and the second power supply line 1100-2. Note that the gate potential of the N-channel transistor 1102 decreases together with the ESD surge.
However, the electrostatic discharge protection circuit shown in FIG. 10 is problematic in that the proportion of a circuit area occupied by the capacitor and the resistive element needs to be increased in order to increase the RC time constant.
FIG. 11 is a diagram showing a configuration of an electrostatic discharge protection circuit proposed by JP-A-2009-182119.
The electrostatic discharge protection circuit shown in FIG. 11, which is connected to a direct-current power supply, includes a first power supply line 1200-1 having a predetermined first potential and a second power supply line 1200-2 having a second potential that is lower than the first potential, as well as a time constant circuit 1210 that includes a capacitor 1212 on the first power supply line 1200-1 side and a first N-channel transistor 1214 on the second power supply line 1200-2 side having a negative threshold voltage, which are connected in series between the first power supply line 1200-1 and the second power supply line 1200-2, an inverter 1220 whose input side is connected to a connection node 1216 located between the capacitor 1212 and the first N-channel transistor 1214 and whose output side is connected to a gate of the first N-channel transistor 1214, and a field effect transistor 1240 that is connected between the first power supply line 1200-1 and the second power supply line 1200-2, whose gate is indirectly connected to the connection node 1216 located between the capacitor 1212 and the first N-channel transistor 1214, and that conducts electricity in response to an increase in the potential of the gate by an increase in the potential of the connection node 1216.
Upon receiving the occurrence of an ESD event, the potential of the connection node 1216 located between the capacitor 1212 and the first N-channel transistor 1214 having a negative threshold increases sharply, and ‘L’ level is output from the inverter 1220. The ‘L’ level is input into the gate of the first N-channel transistor 1214. Accordingly, the value of on-resistance of the first N-channel transistor 1214 is large, and thus the first N-channel transistor 1214 functions as a high resistor that constitutes, together with the capacitor 1212, a RC time constant circuit. Also, the ‘L’ level is indirectly input into the gate of the field effect transistor 1240, and the field effect transistor 1240 is thereby brought into an ON state, which allows the surge current due to the ESD event to escape. As described above, in the invention of JP-A-2009-182119, the N-channel transistor is in the ON state only during a time period corresponding to the value of RC time constant determined by a product between the value of the capacitor 1212 and the value of on-resistance of the N-channel transistor 1214 (for example, a value on the order of several MΩ by input of the ‘L’ level), and the surge current due to the ESD event is discharged during that time period.
The electrostatic discharge protection circuit shown in FIG. 11 is a circuit invented by improving the problems of the electrostatic discharge protection circuit shown in FIG. 10. Although the capacitor size can be reduced, the electrostatic discharge protection circuit shown in FIG. 11 is problematic in that the first N-channel transistor 1214 is a depression type transistor, and thus a step of performing channel doping is required, causing an increase in the cost.
Also, in both FIGS. 10 and 11, the ON time of the N-channel transistor connected between power supply lines is determined by the RC time constant. Therefore, a problem arises in that if ESD events occur sequentially in a short time, for example, electric charges generated by electrostatic discharge are further injected during storage of electric charges into the capacitor, the N-channel transistor is brought into an OFF state while the N-channel transistor is not sufficiently discharged, and the potential increases to cause electric charges to flow into an internal circuit, which may result in breakdown.
Also, in the electrostatic discharge protection circuit shown in FIG. 10, there are three inverters between the capacitor 1101b and the N-channel transistor 1102 connected between the power supply lines. In the electrostatic discharge protection circuit shown in FIG. 11, there are two inverters between the capacitor 1212 and the N-channel transistor 1240. In both of the electrostatic discharge protection circuits, there is a problem in that because it takes time from the reception of the occurrence of an ESD event until the N-channel transistor is turned on, electric charges flow into the internal circuit, which may result in breakdown.